Low on-resistance LDMOS transistors with high breakdown voltages are desirable for their low power loss in high voltage applications. It is well known in the art to increase breakdown voltage by increasing the distance between the drain region and the gate. However, increasing the distance between the drain region and the gate also undesirably increases the on-resistance of the LDMOS transistor.
FIG. 1 is a cross-sectional view of a conventional LDMOS transistor which serves to illustrate some of the causes of the increased on-resistance. In FIG. 1, a P substrate 10 has formed over it an N.sup.- epitaxial layer 11. On the surface of N.sup.- epitaxial layer 11 is formed an oxide layer 12, on which is formed a gate 13. In the surface of the N.sup.- epitaxial layer 11 are formed N.sup.+ drain region 14 and P body region 15. N.sup.+ source region 16 and P.sup.+ body contact region 17 are formed in P body region 15. Source contact 18 contacts both N.sup.+ source region 16 and P.sup.+ body contact region 17. Drain contact 19 contacts N.sup.+ drain region 14.
The distance between N.sup.+ drain region 14 and gate 13 directly affects both on-resistance and breakdown voltage. Since the N.sup.- epitaxial layer 11 between the N.sup.+ drain region 14 and the body region 15 (or gate 13) is only lightly doped, this layer 11 allows a relatively large depletion region to form between the regions 14 and 15 when the MOSFET is off, thus preventing a breakdown of the silicon between the regions 14 and 15. However, the N.sup.- epitaxial layer 11 presents a high resistance between the channel region and the drain region 14 when the MOSFET is turned on. Therefore, in the conventional LDMOS transistor, high breakdown voltage leads to high on-resistance.
What is needed is a novel LDMOS transistor which has a low on-resistance while exhibiting a high breakdown voltage.